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POWER MANAGEMENT Description
Dual Synchronous Buck Pseudo Fixed Frequency Power Supply Controller
Features
Constant on-time for fast dynamic response Programmable VOUT range = 0.5 - VCCA VBAT Range = 1.8V - 25V DC current sense using low-side RDS(ON) sensing or sense resistor Resistor programmable frequency Cycle-by-cycle current limit Digital soft-start Separate PSAVE option for each switcher Over-voltage/Under-voltage fault protection 10A Typical shutdown current Low quiescent power dissipation Two Power Good indicators 1% Reference (2% system DC accuracy) Integrated gate drivers with soft switching Separate enables 28 Lead TSSOP Industrial temperature range Output soft discharge upon shutdown
SC483
The SC483 is a dual output constant-on synchronous buck PWM controller intended for use in notebook computers and other battery operated portable devices. Features include high efficiency and a fast dynamic response with no minimum on time. The excellent transient response means that SC483 based solutions will require less output capacitance than competing fixed frequency converters. The switching frequency is constant until a step in load or line voltage occurs at which time the pulse density and frequency will increase or decrease to counter the change in output or input voltage. After the transient event, the controller frequency will return to steady state operation. At light loads, Power-Save Mode enables the SC483 to skip PWM pulses for better efficiency. Each output voltage can be independently adjusted from 0.5V to VCCA. Two frequency setting resistors set the on-time for each buck controller. The frequency can thus be tailored to minimize crosstalk. The integrated gate drivers feature adaptive shoot-through protection and soft switching. Additional features include cycle-by-cycle current limit, digital soft-start, over-voltage and undervoltage protection, and a PGOOD output for each controller.
VBAT 5VSUS
Applications
Notebook computers CPT I/O supplies Handheld terminals and PDAs LCD monitors Network power supplies
5VSUS VBAT
D1 R1 RTON1 R2 22 10R 23 VOUT1 R3 25 R5 26 27 R7 C5 1nF C6 1uF VSSA1 5VSUS D2 R8 RTON2 R9 8 10R 9 VOUT2 R10 11 R12 12 13 R14 C11 1nF C12 1uF VSSA2 14 FB2 PGD2 VSSA2 VDDP2 DL2 PGND2 17 Q4 16 VSSA2 C10 15 1uF R13 0R VCCA2 ILIM2 18 C9 + 10 EN/PSV2 TON2 VOUT2 BST2 DH2 LX2 21 Q3 20 19 L2 R11 VOUT2 C8 10uF C7 0.1uF 28 FB1 PGD1 VSSA1 VDDP1 DL1 PGND1 3 2 VSSA1 C4 1 1uF Q2 R6 0R VCCA1 ILIM1 4 C3 + 24 U1 EN/PSV1 TON1 VOUT1 SC483 BST1 DH1 LX1 7 Q1 6 5 L1 R4 VOUT1 C2 10uF C1 0.1uF
PGOOD
VBAT
5VSUS
VBAT
PGOOD
Revision: March 14, 2005
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SC483
POWER MANAGEMENT Absolute Maximum Ratings(1)
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability.
Parameter TONn to VSSAn DHn, BSTn to PGNDn LXn to PGNDn PGNDn to VSSAn BSTn to LXn DLn, ILIMn, VDDPn to PGNDn EN/PSVn, FBn, PGDn, VCCAn, VOUTn to VSSAn VCCAn to EN/PSVn, FBn, PGDn, VOUTn Thermal Resistance Junction to Ambient (2) Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec.
Symbol
Maximum -0.3 to +25.0 -0.3 to +30.0 -2.0 to +25.0 -0.3 to +0.3 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +6.0
Units V V V V V V V V C/W C C C
JA TJ TSTG TLEAD
84 -40 to +125 -65 to +150 300
Notes: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required. (2) Measured in accordance with JESD51-1, JESD51-2 and JESD51-7.
Electrical Characteristics
Test Conditions: VBAT = 15V, EN/PSV1=EN/PSV2 = 5V, VCCA1 = VDDP1 = VCCA2 = VDDP2 = 5V, VOUT1 = VOUT2 =1.25V, RTON1 = RTON2 = 1M
Parameter
Conditions Min
25C Typ Max
-40C to 125C Min Max
Units
Input Supplies V C C A 1, V C C A 2 V D D P 1, V D D P 2 VBAT Voltage Offtime > 800ns 1.8 70 700 15 -5 5 0 -10 10 1 5.0 5.0 25 150 1100 4.5 4.5 5.5 5.5 V V V A A A A A A
VDDP1, VDDP2 Operating Current FB > regulation point, ILOAD = 0A VCCA1, VCCA2 Operating Current FB > regulation point, ILOAD = 0A TON1, TON2 Operating Current Shutdown Current RTON = 1M EN/PSV1, EN/PSV2 = 0V V C C A 1, V C C A 2 VDDP1, TON1, VDDP2, TON2
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SC483
POWER MANAGEMENT Electrical Characteristics (Cont.)
Test Conditions: VBAT = 15V, EN/PSV1=EN/PSV2 = 5V, VCCA1 = VDDP1 = VCCA2 = VDDP2 = 5V, VOUT1 = VOUT2 =1.25V, RTON1 = RTON2 = 1M
Parameter
Conditions Min
25C Typ Max
-40C to 125C Min Max
Units
Controller Error Comparator Threshold (FB turn-on threshold)(1) Output Voltage Range On-Time, VBAT = 2.5V RTON = 1M RTON = 500k Minimum Off Time VOUT1, VOUT2 Input Resistance VOUT1, VOUT2 Shutdown Discharge Resistance FB1, FB2 Input Bias Current Over-Current Sensing ILIM Source Current Current Comparator Offset PSAVE Zero-Crossing Threshold Fault Protection Current Limit (Positive) (2) (PGND - LX), RILIM = 5k (PGND - LX), RILIM = 10k (PGND - LX), RILIM = 20k Current Limit (Negative) Output Under-Voltage Fault Output Over-Voltage Fault - OUT1 Output Over-Voltage Fault - OUT2 Over-Voltage Fault Delay PGD Low Output Voltage PGD Leakage Current PGD UV Threshold (PGND - LX) With respect to internal ref. With respect to internal ref. With respect to internal ref. FB forced above OV Threshold Sink 1mA FB in regulation, PGD = 5V With respect to internal ref. -10 -12 50 100 200 -125 -30 +16 +16 5 0.4 1 -8 35 80 170 -160 -40 +12 +12 65 120 230 -90 -25 +20 +20 mV mV mV mV % % % s V A % (PGND - LX), EN/PSV = 5V 5 mV DL high PGND - ILIM 10 9 -10 11 10 A mV EN/PSV1, EN/PSV2 = GND 1761 936 400 500 22 -1.0 +1.0 VCCA = 4.5V to 5.5V 0.500 -1% 0.5 1497 796 +1% VC C A 2025 1076 550 ns k A V V ns
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SC483
POWER MANAGEMENT Electrical Characteristics (Cont.)
Test Conditions: VBAT = 15V, EN/PSV1=EN/PSV2 = 5V, VCCA1 = VDDP1 = VCCA2 = VDDP2 = 5V, VOUT1 = VOUT2 =1.25V, RTON1 = RTON2 = 1M
Parameter
Conditions Min
25C Typ Max
-40C to 125C Min Max
Units
Fault Protection (Cont.) PGD Fault Delay VCCA Undervoltage Threshold Over Temperature Lockout Inputs/Outputs Logic Input Low Voltage Logic Input High Voltage Logic Input High Voltage EN/PSV Input Resistance EN/PSV low EN High, PSV low (Floating) EN/PSV high R Pullup to VCCA R Pulldown to VSSA Soft Start Soft-Start Ramp Time Under-Voltage Blank Time Gate Drivers Shoot-Through Delay (4) DL Pull-Down Resistance DL Sink Current DL Pull-Up Resistance DL Source Current DH Pull-Down Resistance DH Pull-Up Resistance(5) DH Sink/Source Current DH or DL rising DL low DL = 2.5V DL high DL = 2.5V DH low, BST - LX = 5V DH high, BST - LX = 5V DH = 2.5V 30 0.8 3.1 2 1.3 2 2 1.3 4 4 4 1.6 ns A A A EN/PSV high to PGD high EN/PSV high to UV high 440 440 clks(3) clks(3) 1.5 1.0 2.0 3.1 1.2 V V V M FB forced outside PGD window Falling (100mV Hysteresis ) 10C Hysteresis 5 4.0 165 3.7 4.3 s V C
Notes: (1) When the inductor is in continuous and discontinuous conduction mode, the output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the ripple voltage. (2) Using a current sense resistor, this measurement relates to PGND minus the voltage of the source on the lowside MOSFET. These values guaranteed by the ILIM Source Current and Current Comparator Offset tests. (3) clks = Switching cycles. (4) Guaranteed by design. See Shoot-Through Delay Timing Diagram on Page 6. (5) Semtech's SmartDriverTM FET drive first pulls DH high with a pullup resistance of 10 (typ.) until LX = 1.5V (typ.). At this point, an additional pullup device is activated, reducing the resistance to 2 (typ.). This negates the need for an external gate or boost resistor.
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SC483
POWER MANAGEMENT Pin Configuration Ordering Information
Device SC483ITSTRT(2) Package(1) TSSOP-28
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE, RoHS and J-STD-020B compliant.
TSSOP-28
Pin Descriptions
Pin # 1 2 3 4 5 6 7 8 Pin Name PGND1 D L1 VD D P1 ILIM1 LX 1 DH1 BST1 EN/PSV2 Pin Function Power ground. Gate drive output for the low side MOSFET switch. +5V supply voltage input for the gate drivers. Decouple this pin with a 1uF ceramic capacitor to PGND1. Current limit input. Connect to drain of low-side MOSFET for RDS(on) sensing or the source for resistor sensing through a threshold sensing resistor. Phase node (junction of top and bottom MOSFETs and the output inductor) connection. Gate drive output for the high side MOSFET switch. Boost capacitor connection for the high side gate drive. Enable/Power Save input. Pull down to VSSA2 to shut down OUT2 and discharge it through 22 (nom). Pull up to enable OUT2 and activate PSAVE mode. Float to enable OUT2 and activate continuous conduction mode (CCM), which should be used for dynamic voltage transitioning. If floated, bypass to VSSA2 with a 10nF ceramic capacitor. This pin is used to sense VBAT through a pullup resistor, RTON2, and to set the top MOSFET ontime. Bypass this pin with a 1nF ceramic capacitor to VSSA2. Output voltage sense input for output 2. Connect to the output at the load. Supply voltage input for the analog supply. Use a 10 Ohm / 1uF RC filter from 5VSUS to VSSA2. Feedback input. Connect to a resistor divider located at the IC from VOUT2 to VSSA2 to set the output voltage from 0.5V to VCCA2. Power Good open drain NMOS output. Goes high after a fixed clock cycle delay (440 cycles) following power up. Ground reference for analog circuitry. Connect to PGND2 at the bottom of the output capacitor.
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9 10 11 12 13 14
TON2 VOUT2 VC C A2 FB 2 PGD2 VSSA2
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SC483
POWER MANAGEMENT Pin Descriptions (Cont.)
Pin# 15 16 17 18 19 20 21 22 Pin Name PGND2 D L2 VD D P2 ILIM2 LX 2 DH2 BST2 EN/PSV1 Pin Function Power ground. Gate drive output for the low side MOSFET switch. +5V supply voltage input for the gate drivers. Decouple this pin with a 1uF ceramic capacitor to PGND2. Current limit input. Connect to drain of low-side MOSFET for RDS(on) sensing or the source for resistor sensing through a threshold sensing resistor. Phase node (junction of top and bottom MOSFETs and the output inductor) connection. Gate drive output for the high side MOSFET switch. Boost capacitor connection for the high side gate drive. Enable/Power Save input. Pull down to VSSA1 to shut down OUT1 and discharge it through 22 (nom.). Pull up to enable OUT1 and activate PSAVE mode. Float to enable OUT1 and activate continuous conduction mode (CCM). If floated, bypass to VSSA1 with a 10nF ceramic capacitor. This pin is used to sense VBAT through a pullup resistor, RTON1, and to set the top MOSFET ontime. Bypass this pin with a 1nF ceramic capacitor to VSSA1. Output voltage sense input for output 1. Connect to the output at the load. Supply voltage input for the analog supply. Use a 10 Ohm / 1uF RC filter from 5VSUS to VSSA1. Feedback input. Connect to a resistor divider located at the IC from VOUT1 to VSSA1 to set the output voltage from 0.5V to VCCA1. Power Good open drain NMOS output. Goes high after a fixed clock cycle delay (440 cycles) following power up. Ground reference for analog circuitry. Connect to PGND1 at the bottom of the output capacitor.
23 24 25 26 27 28
TON1 VOUT1 VC C A1 FB 1 PGD1 VSSA1
Shoot-Through Delay Timing Diagram
LX
DH
DL DL tplhDL tplhDH
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SC483
POWER MANAGEMENT Block Diagram
VCCA1 (25) EN/SPV1 (22) DSCHG1 BST1 (7) TON1 (23) VOUT1 (24) TON ON OFF PWM DSCHG1 1 OC 1.5V REF + FB1 (26) X3 ZERO I ISENSE ILIM1 (4) VDDP1 (3) DL1 (2) PGND1 (1) OV VSSA1 (28) FAULT MONITOR UV REF + 16% REF - 10% REF - 30% VCCA2 (11) EN/SPV2 (8) DSCHG2 BST2 (21) TON ON OFF PWM DSCHG2 2 TOFF CONTROL LOGIC HI DH2 (20) LX2 (19) POR / SS OT 1 TOFF CONTROL LOGIC HI DH1 (6) LX1 (5)
POR / SS
OT
LO
PGD1 (27)
TON2 (9) VOUT2 (10)
OC 1.5V REF + FB2 (12) X3 ZERO I ISENSE ILIM2 (18) VDDP2 (17) DL2 (16) PGND2 (15) OV VSSA2 (14) FAULT MONITOR UV REF + 16% REF - 10% REF - 30% 2
LO
PGD2 (13)
FIGURE 1.
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SC483
POWER MANAGEMENT Applications Information
+5V Bias Supplies The SC483 requires an external +5V bias supply in addition to the battery. If stand-alone capability is required, the +5V supply can be generated with an external linear regulator such as the Semtech LP2951. To avoid interference between outputs, each controller has its own ground reference, VSSA, which should be tied by a single trace to PGND at the negative terminal of that controller's output capacitor (see Layout Guidelines). All external components referenced to VSSA in the schematic should be connected to the appropriate VSSA trace. The supply decoupling capacitor for controller 1 should be tied between VCCA1 and VSSA1. Likewise, the supply decoupling capacitor for controller 2 should be tied between VCCA2 and VSSA2. A 10 resistor should be used to decouple each VCCA supply from the main VDDP supplies. PGND can then be a separate plane which is not used for routing traces. All PGND connections are connected directly to the ground plane with special attention given to avoiding indirect connections which may create ground loops. As mentioned above, VSSA1 and VSSA2 must be connected to the PGND plane at the negative terminal of their respective output capacitors only. The VDDP1 and VDDP2 inputs provide power to the upper and lower gate drivers. A decoupling capacitor for each supply is required. No series resistor between VDDP and 5V is required. See layout guidelines for more details. Pseudo-fixed Frequency Constant On-Time PWM Controller The PWM control architecture consists of a constant ontime, pseudo fixed frequency PWM controller (see Figure 1, SC483 Block Diagram). The output ripple voltage developed across the output filter capacitor's ESR provides the PWM ramp signal eliminating the need for a current sense resistor. The high-side switch on-time is determined by a one-shot whose period is directly proportional to output voltage and inversely proportional to input voltage. A second one-shot sets the minimum off-time which is typically 400ns. On-Time One-Shot (tON) The on-time one-shot comparator has two inputs. One input looks at the output voltage, while the other input samples the input voltage and converts it to a current.
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This input voltage-proportional current is used to charge an internal on-time capacitor. The on-time is the time required for the voltage on this capacitor to charge from zero volts to VOUT, thereby making the on-time of the high-side switch directly proportional to output voltage and inversely proportional to input voltage. This implementation results in a nearly constant switching frequency without the need for a clock generator. For VOUT < 3.3V:
V t ON = 3.3 x10 -12 * (R TON + 37 x10 3 ) * OUT + 50ns V BAT For 3.3V VOUT 5V:
V t ON = 0.85 * 3.3 x10 -12 * (R TON + 37 x10 3 ) * OUT + 50ns V BAT RTON is a resistor connected from the input supply (VBAT) to the TON pin. Due to the high impedance of this resistor, the TON pin should always be bypassed to VSSA using a 1nF ceramic capacitor.
EN/PSV: Enable, Psave and Soft Discharge The EN/PSV pin enables the supply. When EN/PSV is tied to VCCA the controller is enabled and power save will also be enabled. When the EN/PSV pin is tri-stated, an internal pull-up will activate the controller and power save will be disabled. If PSAVE is enabled, the SC483 PSAVE comparator will look for the inductor current to cross zero on eight consecutive switching cycles by comparing the phase node (LX) to PGND. Once observed, the controller will enter power save and turn off the low side MOSFET when the current crosses zero. To improve light-load efficiency and add hysteresis, the on-time is increased by 50% in power save. The efficiency improvement at light-loads more than offsets the disadvantage of slightly higher output ripple. If the inductor current does not cross zero on any switching cycle, the controller will immediately exit power save. Since the controller counts zero crossings, the converter can sink current as long as the current does not cross zero on eight consecutive cycles. This allows the output voltage to recover quickly in response to negative load steps even when psave is enabled. If the EN/PSV pin is pulled low, the related output will be shut down and discharged using a switch with a nominal resistance of 22 Ohms. This will ensure that the output is in a defined state next time it is enabled and also
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SC483
POWER MANAGEMENT
ensure, since this is a soft discharge, that there are no dangerous negative voltage excursions to be concerned about. In order for the soft discharge circuitry to function correctly, the chip supply must be present. Output Voltage Selection The output voltage (OUT2 shown) is set by the feedback resistors R9 & R13 of Figure 2 below. The internal reference is 1.5V, so the voltage at the feedback pin is multiplied by three to match the 1.5V reference. Therefore the output can be set to a minimum of 0.5V. The equation for setting the output voltage is: The current sensing circuit actually regulates the inductor valley current (see Figure 3). This means that if the current limit is set to 10A, the peak current through the inductor would be 10A plus the peak-to-peak ripple current, and the average current through the inductor would be 10A plus 1/2 the peak-to-peak ripple current. The equations for setting the valley current and calculating the average current through the inductor are shown below: sense element (resistor or MOSFET) falls below the voltage across the RILIM resistor. In an extreme overcurrent situation, the top MOSFET will never turn back on and eventually the part will latch off due to output undervoltage (see Output Undervoltage Protection).
R9 VOUT = 1 + * 0.5 R13
8 9 VOUT VOUT2 C15 56p 0402 R9 20k0 0402 10 11 12 13 R13 14k3 0402 14 EN/PSV2 TON2 VOUT2 VCCA2 FB2 PGD2 VSSA2 U1 BST2 DH2 LX2 ILIM2 VDDP2 DL2 PGND2 21 20 19 18 17 16 15
INDUCTOR CURRENT
IPEAK ILOAD ILIMIT
SC483 OUT2
TIME Valley Current-Limit Threshold Point
VSSA2
Figure 3: Valley Current Limiting Figure 2: Setting The Output Voltage Current Limit Circuit Current limiting of the SC483 can be accomplished in two ways. The on-state resistance of the low-side MOSFET can be used as the current sensing element or sense resistors in series with the low-side source can be used if greater accuracy is desired. RDS(ON) sensing is more efficient and less expensive. In both cases, the RILIM resistor between the ILIM pin and LX pin set the over current threshold. This resistor RILIM is connected to a 10A current source within the SC483 which is turned on when the low side MOSFET turns on. When the voltage drop across the sense resistor or low side MOSFET equals the voltage across the RILIM resistor, positive current limit will activate. The high side MOSFET will not be turned on until the voltage drop across the
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The equation for the current limit threshold is as follows:
ILIMIT = 10e -6 *
RILIM A R SENSE
Where (referring to Figure 8 on Page 16) RILIM is R10 and RSENSE is the RDS(ON) of Q4. For resistor sensing, a sense resistor is placed between the source of Q4 and PGND. The current through the source sense resistor develops a voltage that opposes the voltage developed across RILIM. When the voltage developed across the RSENSE resistor reaches the voltage drop across RILIM, a positive over-current exists and the high side MOSFET will not be allowed to turn on. When using an external sense resistor RSENSE is the resistance of the sense resistor.
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SC483
POWER MANAGEMENT
The current limit circuitry also protects against negative over-current (i.e. when the current is flowing from the load to PGND through the inductor and bottom MOSFET). In this case, when the bottom MOSFET is turned on, the phase node, LX, will be higher than PGND initially. The SC483 monitors the voltage at LX, and if it is greater than a set threshold voltage of 125mV (nom.) the bottom MOSFET is turned off. The device then waits for approximately 2.5s and then DL goes high for 300ns (typ.) once more to sense the current. This repeats until either the over-current condition goes away or the part latches off due to output overvoltage (see Output Overvoltage Protection). Power Good Output The power good output is an open-drain output and requires a pull-up resistor. When the output voltage is 16% above or 10% below its set voltage, PGD gets pulled low. It is held low until the output voltage returns to within these tolerances once more. PGD is also held low during start-up and will not be allowed to transition high until soft start is over (440 switching cycles) and the output reaches 90% of its set voltage. There is a 5s delay built into the PGD circuitry to prevent false transitions. Output Overvoltage Protection When the output exceeds 16% of its set voltage the low-side MOSFET is latched on. It stays latched on and the controller is latched off until reset (see below). There is a 5s delay built into the OV protection circuit to prevent false transitions. Output Undervoltage Protection When the output is 30% below its set voltage the output is latched in a tri-stated condition. It stays latched and the controller is latched off until reset (see below). There is a 5s delay built into the UV protection circuit to prevent false transitions. Note: to reset from any fault, VCCA or EN/PSV must be toggled. POR, UVLO and Softstart An internal power-on reset (POR) occurs when VCCA exceeds 3V, starting up the internal biasing. VCCA undervoltage lockout (UVLO) circuitry inhibits the controller until VCCA rises above 4.2V. At this time the UVLO circuitry resets the fault latch and soft start timer, and allows switching to occur if the device is enabled.
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Switching always starts with DL to charge up the BST capacitor. With the softstart circuit (automatically) enabled, it will progressively limit the output current (by limiting the current out of the ILIM pin) over a predetermined time period of 440 switching cycles. The ramp occurs in four steps: 1) 110 cycles at 25% ILIM with double minimum off-time (for purposes of the on-time one-shot, there is an internal positive offset of 120mV to VOUT during this period to aid in startup) 2) 110 cycles at 50% ILIM with normal minimum off-time 3) 110 cycles at 75% ILIM with normal minimum off-time 4) 110 cycles at 100% ILIM with normal minimum off-time. At this point the output undervoltage and power good circuitry is enabled. There is 100mV of hysteresis built into the UVLO circuit and when VCCA falls to 4.1V (nom.) the output drivers are shut down and tristated. MOSFET Gate Drivers The DH and DL drivers are optimized for driving moderate-sized high-side, and larger low-side power MOSFETs. An adaptive dead-time circuit monitors the DL output and prevents the high-side MOSFET from turning on until DL is fully off (below ~1V). Semtech's SmartDriverTM FET drive first pulls DH high with a pull-up resistance of 10 (typ.) until LX = 1.5V (typ.). At this point, an additional pull-up device is activated, reducing the resistance to 2 (typ.). This negates the need for an external gate or boost resistor. The adaptive dead-time circuit also monitors the phase node, LX, to determine the state of the high side MOSFET, and prevents the lowside MOSFET from turning on until DH is fully off (LX below ~1V). Be sure to have low resistance and low inductance between the DH and DL outputs to the gate of each MOSFET. Dropout Performance The output voltage adjust range for continuousconduction operation is limited by the fixed 550ns (maximum) minimum off-time one-shot. For best dropout performance, use the slowest on-time setting of 200kHz. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. The IC duty-factor limitation is given by:
DUTY =
t ON( MIN ) t ON( MIN )
+ t OFF(MAX )
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SC483
POWER MANAGEMENT
Be sure to include inductor resistance and MOSFET onstate voltage drops when performing worst-case dropout duty-factor calculations. SC483 System DC Accuracy Two IC parameters affect system DC accuracy, the error comparator threshold voltage variation and the switching frequency variation with line and load. The error comparator threshold does not drift significantly with supply and temperature. Thus, the error comparator contributes 1% or less to DC system inaccuracy. Board components and layout also influence DC accuracy. The use of 1% feedback resistors contribute 1%. If tighter DC accuracy is required use 0.1% feedback resistors. The on pulse in the SC483 is calculated to give a pseudo fixed frequency. Nevertheless, some frequency variation with line and load can be expected. This variation changes the output ripple voltage. Because constant-on regulators regulate to the valley of the output ripple, 1/2 of the output ripple appears as a DC regulation error. For example, if the feedback resistors are chosen to divide down the output by a factor of five, the valley of the output ripple will be VOUT. For example: if VOUT is 2.5V and the ripple is 50mV with VBAT = 6V, then the measured DC output will be 2.525V. If the ripple increases to 80mV with VBAT = 25V, then the measured DC output will be 2.540V. The output inductor value may change with current. This will change the output ripple and thus the DC output voltage. It will not change the frequency. Switching frequency variation with load can be minimized by choosing MOSFETs with lower R DS(ON). High R DS(ON) MOSFETs will cause the switching frequency to increase as the load current increases. This will reduce the ripple and thus the DC output voltage. Design Procedure Prior to designing an output and making component selections, it is necessary to determine the input voltage range and the output voltage specifications. For purposes of demonstrating the procedure the output for the schematic in Figure 8 on Page 16 will be designed.
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The maximum input voltage (VBAT(MAX)) is determined by the highest AC adaptor voltage. The minimum input voltage (V BAT(MIN)) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. For the purposes of this design example we will use a VBAT range of 8V to 20V and design OUT2. The design for OUT1 employs the same technique. Four parameters are needed for the output: 1) nominal output voltage, VOUT (we will use 1.2V) 2) static (or DC) tolerance, TOLST (we will use +/-4%) 3) transient tolerance, TOLTR and size of transient (we will use +/-8% and 6A for purposes of this demonstration). 4) maximum output current, IOUT (we will design for 6A) Switching frequency determines the trade-off between size and efficiency. Increased frequency increases the switching losses in the MOSFETs, since losses are a function of VIN2. Knowing the maximum input voltage and budget for MOSFET switches usually dictates where the design ends up. It is recommended that the two outputs are designed to operate at frequencies approximately 25% apart to avoid any possible interaction. It is also recommended that the higher frequency output is the lower output voltage output, since this will tend to have lower output ripple and tighter specifications. The default RtON values of 1M and 715k are suggested as a starting point, but these are not set in stone. The first thing to do is to calculate the on-time, tON, at VBAT(MIN) and VBAT(MAX), since this depends only upon VBAT, VOUT and R tON. For VOUT < 3.3V:
VOUT -9 t ON _ VBAT(MIN) = 3.3 * 10 -12 * (R tON + 37 * 103 ) * + 50 * 10 s VBAT (MIN)
and
VOUT -9 t ON _ VBAT (MAX ) = 3.3 * 10 -12 * (R tON + 37 * 10 3 ) * + 50 * 10 s VBAT (MAX )
From these values of tON we can calculate the nominal switching frequency as follows:
fSW _ VBAT (MIN ) =
and
(V
VOUT Hz BAT ( MIN ) * t ON _ VBAT ( MIN ) )
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SC483
POWER MANAGEMENT
fSW _ VBAT (MAX ) VOUT = (VBAT(MAX ) * t ON _ VBAT(MAX ) )Hz
From this we can calculate the minimum inductor current rating for normal operation:
tON is generated by a one-shot comparator that samples VBAT via RtON, converting this to a current. This current is used to charge an internal 3.3pF capacitor to VOUT. The equations above reflect this along with any internal components or delays that influence tON. For our example we select RtON = 1M: tON_VBAT(MIN) = 563ns and tON_VBAT(MAX) = 255ns fSW_VBAT(MIN) = 266kHz and fSW_VBAT(MAX) = 235kHz Now that we know tON we can calculate suitable values for the inductor. To do this we select an acceptable inductor ripple current. The calculations below assume 50% of IOUT which will give us a starting place.
IINDUCTOR (MIN) = IOUT (MAX ) +
For our example: IINDUCTOR(MIN) = 7.1A(MIN)
IRIPPLE _ VBAT (MAX ) 2
A (MIN)
Next we will calculate the maximum output capacitor equivalent series resistance (ESR). This is determined by calculating the remaining static and transient tolerance allowances. Then the maximum ESR is the smaller of the calculated static ESR (R ESR_ST(MAX)) and transient ESR (R ESR_TR(MAX)):
RESR _ ST (MAX ) =
(ERR
ST
- ERRDC ) * 2
IRIPPLE _ VBAT (MAX )
Ohms
L VBAT (MIN) = (VBAT (MIN) - VOUT ) *
and
t ON _ VBAT (MIN)
OUT
(0.5 * I )
H
Where ERRST is the static output tolerance and ERRDC is the DC error. The DC error will be 1% plus the tolerance of the feedback resistors, thus 2% total for 1% feedback resistors. For our example: ERRST = 48mV and ERRDC = 24mV, therefore RESR_ST(MAX) = 22m
L VBAT (MAX ) = (VBAT (MAX ) - VOUT ) *
For our example:
t ON _ VBAT (MAX )
(0.5 * I )
OUT
H
LVBAT(MIN) = 1.3H and LVBAT(MAX) = 1.6H We will select an inductor value of 2.2H to reduce the ripple current, which can be calculated as follows:
RESR _ TR (MAX ) =
(ERR
IOUT
IRIPPLE _ VBAT (MIN) = (VBAT (MIN) - VOUT ) *
and
t ON _ VBAT (MIN) L
A P -P
TR - ERR DC ) Ohms IRIPPLE _ VBAT (MAX ) + 2
IRIPPLE _ VBAT (MAX ) = (VBAT (MAX ) - VOUT ) *
t ON _ VBAT (MAX ) L
Where ERRTR is the transient output tolerance. Note that this calculation assumes that the worst case load transient is full load. For half of full load, divide the IOUT term by 2. For our example: ERRTR = 96mV and ERRDC = 24mV, therefore RESR_TR(MAX) = 10.2m for a full 6A load transient
A P -P
For our example: IRIPPLE_VBAT(MIN) = 1.74AP-P and IRIPPLE_VBAT(MAX) = 2.18AP-P
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POWER MANAGEMENT
We will select a value of 12.5m maximum for our design, which would be achieved by using two 25m output capacitors in parallel. Note that for constant-on converters there is a minimum ESR requirement for stability which can be calculated as follows: For our example we will use R TOP = 20.0k and RBOT = 14.3k, therefore: ZTOP = 6.67k and CTOP = 60pF We will select a value of CTOP = 56pF. Calculating the value of VFB based upon the selected CTOP:
R BOT = VRIPPLE _ VBAT(MIN) * 1 RBOT + 1 + 2 * * fSW _ VBAT(MIN) * C TOP R TOp VP -P
RESR (MIN )
3 = 2 * * COUT * fSW
This criteria should be checked once the output capacitance has been determined. Now that we know the output ESR we can calculate the output ripple voltage:
VFB _ VBAT(MIN)
VRIPPLE _ VBAT(MAX) = RESR * IRIPPLE _ VBAT(MAX) VP -P
and
For our example: VFB_VBAT(MIN) = 14.8mVP-P - good Next we need to calculate the minimum output capacitance required to ensure that the output voltage does not exceed the transient maximum limit, POSLIMTR, starting from the actual static maximum, VOUT_ST_POS, when a load release occurs:
VRIPPLE _ VBAT(MIN) = RESR * IRIPPLE _ VBAT(MIN) VP -P
For our example: VRIPPLE_VBAT(MAX) = 27mVP-P and VRIPPLE_VBAT(MIN) = 22mVP-P Note that in order for the device to regulate in a controlled manner, the ripple content at the feedback pin, VFB, should be approximately 15mVP-P at minimum V BAT , and worst case no smaller than 10mV P-P . If VRIPPLE_VBAT(MIN) is less than 15mVP-P the above component values should be revisited in order to improve this. Quite often a small capacitor, CTOP, is required in parallel with the top feedback resistor, RTOP, in order to ensure that V FB is large enough. C TOP should not be greater than 100pF. The value of CTOP can be calculated as follows, where R BOT is the bottom feedback resistor. Firstly calculating the value of ZTOP required:
VOUT _ ST _ POS = VOUT + ERRDC V
For our example: VOUT_ST_POS = 1.224V
POSLIM TR = VOUT * TOL TR V
Where TOLTR is the transient tolerance. For our example: POSLIMTR = 1.296V The minimum output capacitance is calculated as follows:
I IOUT + RIPPLE _ VBAT (MAX ) 2 =L* F 2 2 POSLIM TR - VOUT _ ST _ POS
2
Z TOP
R = BOT * (VRIPPLE _ VBAT (MIN) - 0.015 )Ohms 0.015
Secondly calculating the value of CTOP required to achieve this:
1 1 - Z TOP R TOP F = 2 * * fSW _ VBAT (MIN)
C OUT (MIN)
(
)
C TOP
This calculation assumes the absolute worst case condition of a full-load to no load step transient occurring when the inductor current is at its highest. The capacitance required for smaller transient steps my be calculated by substituting the desired current for the IOUT term.
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POWER MANAGEMENT
For our example: COUT(MIN) = 610F. We will select 440F, using two 220F, 25m capacitors in parallel. For smaller load release overshoot, 660F may be used. Next we calculate the RMS input ripple current, which is largest at the minimum battery voltage: Thermal Considerations The junction temperature of the device may be calculated as follows:
TJ = TA + PD * JA C
IIN(RMS ) = VOUT * (VBAT (MIN) - VOUT ) *
For our example: IIN(RMS) = 2.14ARMS
IOUT VBAT _ MIN
A RMS
Where: TA = ambient temperature (C) PD = power dissipation in (W) JA = thermal impedance junction to ambient from absolute maximum ratings (C/W) The power dissipation may be calculated as follows:
PD = 2 * (VCCA * IVCCA + VDDP * IVDDP ) + Vg * Q g1 * f1 + VBST * 1mA * D1 + Vg * Q g2 * f2 + VBST * 1mA * D 2 W
Input capacitors should be selected with sufficient ripple current rating for this RMS current, for example a 10F, 1210 size, 25V ceramic capacitor can handle approximately 3A RMS . Refer to manufacturer's data sheets and derate appropriately. Finally, we calculate the current limit resistor value. As described in the current limit section, the current limit looks at the "valley current", which is the average output current minus half the ripple current. We use the maximum room temperature specification for MOSFET RDS(ON) at VGS = 4.5V for purposes of this calculation:
Where: VCCA = chip supply voltage (V) IVCCA = operating current (A) VDDP = gate drive supply voltage (V) IVDDP = gate drive operating current (A) Vg = gate drive voltage, typically 5V (V) Qgx = FET gate charge, from the FET datasheet (C) fx = switching frequency (kHz) VBST = boost pin voltage during tON (V) Dx = duty cycle Inserting the following values for VBAT(MIN) condition (since this is the worst case condition for power dissipation in the controller) as an example (OUT1 = 1.5V, OUT2 = 1.2V): TA = 85C JA = 84C/W VCCA = VDDP = 5V IVCCA = 1100A (data sheet maximum) IVDDP = 150A (data sheet maximum) Vg = 5V Qgx = 60nC f1 = 250kHz f2 = 300kHz VBAT(MIN) = 8V VBST(MIN) = VBAT(MIN)+VDDP = 13V D1(MIN) = 1.5/8 = 0.1875 D2(MIN) = 1.2/8 = 0.15
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IVALLEY = IOUT -
IRIPPLE _ VBAT (MIN) 2
A
The ripple at low battery voltage is used because we want to make sure that current limit does not occur under normal operating conditions.
RILIM = (IVALLEY * 1.2) *
For our example:
RDS( ON) * 1.4 10 * 10 - 6
Ohms
IVALLEY = 5.13A, RDS(ON) = 9m and RILIM = 7.76k We select the next lowest 1% resistor value: 7.68k
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POWER MANAGEMENT
gives us:
PD = 2 * (5 * 1100 * 10 -6 + 5 * 150 * 10 -6 ) + 5 * 60 * 10 -9 * 250 * 10 3 + 13 * 1 * 10 -3 * 0.1875 + 5 * 60 * 10 -9 * 300 * 103 + 13 * 1 * 10 -3 * 0.15 = 0.182 W
and:
TJ = 85 + 0.182 * 84 = 100 C
As can be seen, the heating effects due to internal power dissipation are practically negligible, thus requiring no special consideration thermally during layout.
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POWER MANAGEMENT
Layout Guidelines One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and maximize heat dissipation. The IC ground references, VSSA1 and VSSA2, should be kept separate from power ground. All components that are referenced to them should connect to them locally at the chip. VSSA1 and VSSA2 should connect to power ground at their respective output capacitors only. Feedback traces must be kept far away from noise sources such as switching nodes, inductors and gate drives. Route feedback traces with their respective VSSAs as a differential pair from the output capacitor back to the chip. Run them in a "quiet layer" if possible. Chip decoupling capacitors (VDDP, VCCA) should be located next to the pins and connected directly to them on the same side. Power sections should connect directly to the ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). Power components should be placed to minimize loops and reduce losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not use "minimum" land patterns for power components. Minimize trace lengths between the gate drivers and the gates of the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most critical. Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling requirement (and to reduce parasitics) if routed on more than one layer Current sense connections must always be made using Kelvin connections to ensure an accurate signal. We will examine the SC483 OUT2 reference design used in the Design Procedure section while explaining the layout guidelines in more detail, using the same generic components for OUT1.
5VSUS VBAT 5VSUS D1 SOD323 C5 0.1uF 0603
VBAT
R1 1M 0402
R2 10R 0402
22 23
U1 EN/PSV1 TON1 VOUT1 VCCA1 FB1 PGD1 VSSA1
SC483 BST1 DH1 LX1 ILIM1 VDDP1 DL1 PGND1
7 6 5 4 3 2 1 C10 1uF 0603
Q2 IRF7811AV
C6 2n2/50V 0402 L1 2u2
C1 0u1/25V 0603
C2 10u/25V 1210
VOUT1 VOUT C7 56p 0402 R4 20k0 0402
24 25 26 27
R5 7k87 0402
VOUT1 C8 + Q1 FDS6676S R6 0R (1) 0402 220u/25m 7343 + 220u/25m 7343 C3
PGOOD R3 20k0 0402
C4 1nF 0402
C9 1uF 0603
28
VSSA1
VSSA1 VBAT 5VSUS
5VSUS
VBAT
R7 1M 0402
R8 10R 0402
8 9
EN/PSV2 TON2 VOUT2 VCCA2 FB2 PGD2 VSSA2
BST2 DH2 LX2 ILIM2 VDDP2 DL2 PGND2
21 20 19 18 17 16 15 C20 1uF 0603
D2 SOD323 C11 0.1uF 0603
Q3 IRF7811AV
C12 2n2/50V 0402 L2 2u2
C13 0u1/25V 0603
C14 10u/25V 1210
VOUT2 VOUT C15 56p 0402 R9 20k0 0402
10 11 12 13
R10 7k87 0402
VOUT2 C16 + Q4 FDS6676S R12 0R (1) 0402 220u/25m 7343 + 220u/25m 7343 C17
PGOOD R13 20k0 0402
C18 1nF 0402
C19 1uF 0603
14
VSSA2
VSSA2
N OTES (1) R 6 and R 12 aid in k eeping VSSA1 and VSSA2 s eparate f rom PGN D ex c ept where des ired in lay out.
Figure 8: Reference Design and Layout Example
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SC483
POWER MANAGEMENT
The layout can be considered in two parts, the control section referenced to VSSA1/2 and the power section. Looking at the control section first, locate all components referenced to VSSA1/2 on the schematic and place these components at the chip. Connect VSSA1 and VSSA2 using either a wide (>0.020") trace. Very little current flows in the chip ground therefore large areas of copper are not needed.
5VSUS VBAT 5VSUS
R1 0402
R2 10R 0402
22 23
U1 EN/PSV1 TON1 VOUT1 VCCA1 FB1 PGD1 VSSA1
SC483 BST1 DH1 LX1 ILIM1 VDDP1 DL1 PGND1
7 6 5 4 3 2 1 C10 1uF 0603
VOUT1 VOUT C7 0402 R4 0402
24 25 26 27
PGOOD R3 C4 1nF 0402 0402 C9 1uF 0603
28
VSSA1 VBAT 5VSUS
5VSUS
R7 1M 0402
R8 10R 0402
8 9
EN/PSV2 TON2 VOUT2 VCCA2 FB2 PGD2 VSSA2
BST2 DH2 LX2 ILIM2 VDDP2 DL2 PGND2
21 20 19 18 17 16 15 C20 1uF 0603
VOUT VOUT2 C15 56p 0402 R9 20k0 0402
10 11 12 13
PGOOD R13 20k0 0402
C18 1nF 0402
C19 1uF 0603
14
VSSA2
Figure 9: Components Connected to VSSA1 and VSSA2
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POWER MANAGEMENT
Figure 10: Example VSSA 0.020" Traces In Figure 10, all components referenced to VSSA1 and VSSA2 have been placed and have been connected using 0.020" traces. Note that there are two separate traces, one for VSSA1 and one for VSSA2. Decoupling capacitors C9 and C19 are as close as possible to their pins, as are VDDP decoupling capacitors C10 and C20. C10 and C20 should connect to the ground plane using two vias each.
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POWER MANAGEMENT
VOUT1 VSSA1
U1 22 23 VOUT1 VOUT C7 0402 R4 0402 24 25 26 27 R3 0402 28 EN/PSV1 TON1 VOUT1 VCCA1 FB1 PGD1 VSSA1
SC483 BST1 DH1 LX1 ILIM1 VDDP1 DL1 PGND1 7 6 5 4 + 3 2 1 VSSA1 R6 0R (2) 7343 0402 7343 VOUT1 C8 + C3
VSSA1
8 9 VOUT2 VOUT C15 56p 0402 R9 20k0 0402 10 11 12 13 R13 20k0 0402 14
EN/PSV2 TON2 VOUT2 VCCA2 FB2 PGD2 VSSA2
BST2 DH2 LX2 ILIM2 VDDP2 DL2 PGND2
21 20 19 18 C16 + 17 16 0402 15 VSSA2 R12 0R (2) 220u/25m 7343 + 220u/25m 7343 C17 VOUT2
VSSA2 VOUT2 VSSA2
Figure 11: Differential Routing of Feedback and Ground Reference Traces In Figure 11, VOUT1 and VSSA1 are routed as a differential pair from the output capacitors back to the feedback components and device. Similarly, VOUT2 and VSSA2 are routed as a differential pair from the output capacitors back to the feedback components and device.
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POWER MANAGEMENT
Next, looking at the power section, the schematic in Figure 12 below shows the power section and input loop for OUT2:
VBAT 8 7 6 5 Q3 IRF7811AV 1 D S2 D S3 D S4 D G
L2
2u2 VOUT2 C16 + R12 0R (2) 0402 220u/25m 7343 + 220u/25m 7343 C17
C14 10u/25V 1210
C13 0u1/25V 0603
C12 2n2/50V 0402 4 3 2 1 Q4 FDS6676S 5 G D 6 S D 7 S D 8 S D
Figure 12: Power Section and Input Loop The schematic has been redrawn to emphasize the input loop. The highest di/dts occur in the input loops and thus these should be kept as small as possible. The input capacitors should be placed with the highest frequency capacitors closest to the loop to reduce EMI. Use large copper pours to minimize losses and parasitics. Exactly the same philosophy applies to the OUT1 power section and input loop. Figure 13 below shows an example of the layout for the power section using these guidelines.
Figure 13: Power Component Placement and Copper Pours
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POWER MANAGEMENT
Key points for the power section: 1) there should be a very small input loop, well decoupled. 2) the phase node should be a large copper pour, but compact since this is the noisiest node. 3) input power ground and output power ground should not connect directly, but through the ground planes instead. 4) The two outputs should not share their input capacitors, and these should have separate PWR_SRC and PGND (component-side) copper pours. 5) The two output inductors should not be placed adjacent to each other to avoid crosstalk. 6) Notice in Figure 13 placement of 0 resistor at the bottom of the output capacitor to connect to VSSA1/2 for each output. Connecting the control and power sections should be accomplished as follows (see Figure 14 below): 1) Route VSSA1/2 and their related feedback traces as differential pairs routed in a "quiet" layer away from noise sources. 2) Route DL, DH and LX (low side FET gate drive, high side FET gate drive and phase node) to chip using wide traces with multiple vias if using more than one layer. These connections to be as short as possible for loop minimization, with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power ground as its return path. LX is the noisiest node in the circuit, switching between PWR_SRC and ground at high frequencies, thus should be kept as short as practical. DH has LX as its return path. 3) BST is also a noisy node and should be kept as short as possible. 4) Connect PGND pins on the chip directly to the VDDP decoupling capacitor and then drop vias directly to the ground plane. 5) Locate the current limit sense resistors between the LX and ILIM pins at the device.
22 23 24 25 26 27 28
U1 EN/PSV1 TON1 VOUT1 VCCA1 FB1 PGD1 VSSA1
SC483 BST1 DH1 LX1 ILIM1 VDDP1 DL1 PGND1
7 6 5 4 3 2 1 R5 0402
Q2
L1
Q1
8 9 10 11 12 13 14
EN/PSV2 TON2 VOUT2 VCCA2 FB2 PGD2 VSSA2
BST2 DH2 LX2 ILIM2 VDDP2 DL2 PGND2
21 20 19 R10 7k87 18 0402 17 16 15
Q3 IRF7811AV
L2
2u2
Q4 FDS6676S
Figure 14: Connecting Control and Power Sections Phase nodes (black) to be copper islands (preferred) or wide copper traces. Gate drive traces (red) and phase node traces (blue) to be wide copper traces (L:W < 20:1) and as short as possible, with DL the most critical.
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SC483
POWER MANAGEMENT Typical Characteristics
1.2V Efficiency (Power Save Mode) vs. Output Current vs. Input Voltage
100 95 90 85 Efficiency (%) 80 75 70 65 60 55 50 0 1 2 3 IOUT (A) 4 5 6 Efficiency (%) VBAT = 20V VBAT = 8V
1.2V Efficiency (Continuous Conduction Mode) vs. Output Current vs. Input Voltage
100 95 90 85 80 75 70 65 60 55 50 0 1 2 3 IOUT (A) 4 5 6 VBAT = 20V VBAT = 8V
1.2V Output Voltage (Power Save Mode) vs. Output Current vs. Input Voltage
1.220 1.216 1.212 1.208 VOUT (V) 1.204 1.200 1.196 1.192 1.188 1.184 1.180 0 1 2 3 IOUT (A) 4 5 6 VBAT = 8V VBAT = 20V
1.2V Output Voltage (Continuous Conduction Mode) vs. Output Current vs. Input Voltage
1.220 1.216 1.212 1.208 VOUT (V) 1.204 1.200 1.196 1.192 1.188 1.184 1.180 0 1 2 3 IOUT (A) 4 5 6 VBAT = 8V VBAT = 20V
1.2V Switching Frequency (Power Save Mode) vs. Output Current vs. Input Voltage
400 VBAT = 8V 350 300 Frequency (kHz) 250 200 150 100 50 0 0 1 2 3 IOUT (A) 4 5 6
1.2V Switching Frequency (Continuous Conduction Mode) vs. Output Current vs. Input Voltage
400 VBAT = 8V 350 300 Frequency (kHz)
VBAT = 20V
250 200 150 100 50 0 0 1 2
VBAT = 20V
3 IOUT (A)
4
5
6
Please refer to Figure 8 on Page 16 for test schematic (OUT2)
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SC483
POWER MANAGEMENT Typical Characteristics (Cont.)
Load Transient Response, Continuous Conduction Mode, 0A to 6A to 0A Trace 1: 1.2V, 50mV/div., AC coupled Trace 2: LX, 20V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 40s/div.
Load Transient Response, Continuous Conduction Mode, 0A to 6A Zoomed Trace 1: 1.2V, 20mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 10s/div.
Load Transient Response, Continuous Conduction Mode, 6A to 0A Zoomed Trace 1: 1.2V, 50mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 10s/div.
Please refer to Figure 8 on Page 16 for test schematic (OUT2)
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SC483
POWER MANAGEMENT Typical Characteristics (Cont.)
Load Transient Response, Power Save Mode, 0A to 6A to 0A Trace 1: 1.2V, 50mV/div., AC coupled Trace 2: LX, 20V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 40s/div.
Load Transient Response, Power Save Mode, 0A to 6A Zoomed Trace 1: 1.2V, 20mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 10s/div.
Load Transient Response, Power Save Mode, 6A to 0A Zoomed Trace 1: 1.2V, 50mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 10s/div.
Please refer to Figure 8 on Page 16 for test schematic (OUT2)
2005 Semtech Corp. 24 www.semtech.com
SC483
POWER MANAGEMENT Typical Characteristics (Cont.)
Startup (PSV), EN/PSV Going High Trace 1: 1.2V, 0.5V/div. Trace 2: LX, 10V/div Trace 3: EN/PSV, 5V/div Trace 4: PGD, 5V/div. Timebase: 1ms/div.
Startup (CCM), EN/PSV 0V to Floating Trace 1: 1.2V, 0.5V/div. Trace 2: LX, 10V/div Trace 3: EN/PSV, 5V/div Trace 4: PGD, 5V/div. Timebase: 1ms/div.
Please refer to Figure 8 on Page 16 for test schematic (OUT2)
2005 Semtech Corp. 25 www.semtech.com
SC483
POWER MANAGEMENT Outline Drawing - TSSOP-28
A e N 2X E/2 E1 PIN 1 INDICATOR ccc C 2X N/2 TIPS 123
D
DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX
A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc .047 .002 .006 .031 .042 .007 .012 .003 .007 .378 .382 .386 .169 .173 .177 .252 BSC .026 BSC .018 .024 .030 (.039) 28 0 8 .004 .004 .008 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 9.60 9.70 9.80 4.30 4.40 4.50 6.40 BSC 0.65 BSC 0.45 0.60 0.75 (1.0) 28 0 8 0.10 0.10 0.20
E
e/2 B D A2 A
aaa C SEATING PLANE
C
bxN bbb
A1 C A-B D GAGE PLANE 0.25
H c
L (L1) DETAIL
01
SIDE VIEW
SEE DETAIL
A
A
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AE.
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SC483
POWER MANAGEMENT Land Pattern - TSSOP-28
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.222) .161 .026 .016 .061 .283 (5.65) 4.10 0.65 0.40 1.55 7.20
Y P
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
2005 Semtech Corp. 27 www.semtech.com

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